1. Field of the Invention
The present invention relates generally to microprocessors and operating systems.
2. Description of the Background Art
In general, when a central processing unit (CPU) of a computer system receives an interrupt, the CPU suspends its current operations, saves the status of its work, and transfers control to a special routine that contains the instructions for dealing with the particular situation that caused the interrupt. Interrupts might be generated by various hardware devices to request service or to report problems, or by the CPU itself in response to program errors or requests for operating system services. Interrupts are the CPU's way of communicating with the other elements that make up the computer system. A hierarchy of interrupt priorities determines which interrupt request will be handled first, if more than one request has been made. Particular programs can temporarily disable some interrupts, when the program needs the full attention of the processor to complete a particular task.
An interrupt can be considered a feature of a computer that permits the execution of one program to be interrupted in order to execute another program. That other program might be a special program that is executed when a specific interrupt occurs, sometimes called an interrupt handler. Interrupts from different causes have different handlers to carry out the corresponding tasks, such as updating the system clock or reading the keyboard. A table stored in memory contains pointers, sometimes called address vectors, which direct the CPU to the various interrupt handlers. Programmers can create interrupt handlers to replace or supplement existing handlers. Alternatively, that other program might be one that takes place only when requested by means of an interrupt, sometimes called an interrupt-driven process. After the required task has been completed, the CPU is then free to perform other tasks until the next interrupt occurs. Interrupt driven processors sometimes are used to respond to such events as a floppy-disk drive having become ready to transfer data.
Computers typically include a hardware line, sometimes called an interrupt request line, over which devices such as a keyboard or a disk drive can send interrupts to the CPU. Such interrupt request lines are built into the computer's internal hardware, and are assigned different levels of priority so that the CPU can determine the sources and relative importance of incoming service requests. The manner in which a particular computer deals with interrupts, is determined by the computer's interrupt controller. Early interrupt controllers were hard-wired in the computer. As such, their operation was fixed by the computer manufacturer, and could not be altered. More recent interrupt controllers are typically programmable.
In certain microprocessors manufactured by Intel Corporation of Santa Clara, Calif., an advanced programmable interrupt controller (APIC) is included in the CPU. The recently introduced Itanium™ microprocessor, also manufactured by Intel Corporation, is a CPU under the Intel IPF processor architecture. The IPF architecture includes a streamlined advanced programmable interrupt controller (SAPIC). Both the APIC and the SAPIC include a local mask register called a task priority register (TPR) that has eight bits to designate up to 256 priority states, although some of them are reserved. The data in the TPR is changed to reflect the level of priority of the tasks being performed by the processor.
FIG. 1 illustrates a schematic diagram of an example computer system implementing a SAPIC interrupt routing scheme. The computer system 100 may include a single processor 101, as shown, or a plurality of processors. The processor 101 may be, for example, a CPU from Intel Corporation, such as one with the Intel IPF processor architecture. The processor 101 is coupled to a bus 110 that transmits data signals between the processor 101 and other components in the computer system 100.
The memory 113 may comprise a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and/or other memory devices. The memory 113 stores data signals that may be executed by the processor 101. A bridge memory controller 111 is coupled to the bus 110 and the memory 113. The bridge memory controller 111 directs data traffic between the processor 101, the memory 113, and other components in the computer system 100 and bridges signals from these components to a high-speed input/output (I/O) bus 120.
The computer system 100 includes a bus bridge 123 configured to deliver interrupts using the SAPIC interrupt delivery scheme. The bus bridge 123 is connected to the peripheral devices on the I/O bus 130 via a plurality of interrupt request (“IRQ”) lines 163-165. A first IRQ line 163 connects the bus bridge 123 with the data storage device 131. A second IRQ line 164 connects the bus bridge 123 with the keyboard interface 132. A third IRQ line 165 connects the bus bridge 123 with the audio controller. When a peripheral on the I/O bus 130 requires the processor 101 to perform a service, the peripheral device transmits an interrupt request to the bus bridge 123 by asserting its corresponding IRQ line. The bus bridge 123 forwards the interrupt to the interrupt router 140 coupled to the high speed I/O bus 120 via one of the plurality of IRQ lines 154. The interrupt router 140 reformats the interrupt into an interrupt message and transmits the interrupt message over the high speed I/O bus 120. Interrupt messages are transmitted as posted memory writes from the high speed I/O bus 120 to the CPU bus 110.
The interrupt router is connected to peripherals on the high speed I/O bus 120 via a plurality of Peripheral Component Interconnect interrupt request lines (“PIRQ”) 161-162. A first PIRQ line 161 connects the network controller 121 to the interrupt router 140. A second PIRQ line 162 connects the display device controller 122 to the interrupt router 140. When a peripheral on the high speed I/O bus 120 requires the processor 101 to perform a service, the peripheral device transmits an interrupt request to the interrupt router 140 by asserting its corresponding PIRQ line. The interrupt router 140 reformats the interrupt into an interrupt message and transmits the interrupt message over the high speed I/O bus 120. Interrupt messages are transmitted as posted memory writes from the high speed I/O bus 120 to the CPU bus 110.
FIG. 2 is a flow diagram depicting a logical process where a task priority register (TPR) is utilized under the SAPIC architecture of an Intel IPF processor. The flow diagram is entered via the line 210 in response to an Interrupt Vector Register (IVR) being read. The first illustrated control action is determining whether a non-maskable interrupt is present (the decision block 220). If a non-maskable interrupt is present, it is returned in the IVR (the process block 230).
If, on the other hand, a non-maskable interrupt is not present, then the decision block 240 is entered. The decision is made whether the TPR has disabled the interrupts present, or, whether the Highest Pending Interrupt (HPI) is less than, or equal to, the Highest Servicing Interrupt (HSI). If the result of the decision block 240 is yes, then the spurious vector is returned in the IVR (process block 250). For example, in one implementation, a specific vector number is reserved to indicate a spurious vector. With respect to decision block 240, note that HPI might equal HSI because, in operation, an interrupt source might send an interrupt to the controller while the controller is in the process of service an interrupt previously received from that device, or more than one interrupt source might be programmed with the same interrupt vector.
If the outcome of the decision block 240 is no, that is, if TPR has not disabled the interrupts present and HPI is greater than HSI, then the Interrupt Service Register (ISR) bit corresponding to the highest priority interrupt, which in one implementation is the top-most vector in the Interrupt Request Register (IRR), is set. In addition, the IRR bit corresponding to the highest priority interrupt is cleared. Also, the top-most vector (the vector for the highest priority interrupt) in the IRR is returned in the IVR.